Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on leakage current CMOS integrated circuits. It shown that frequency dependence can be easily described by transfer function depends only few dominant parasitic elements. The analytical successfully compared against measurement data from devices fabricated using 180 nm, 130 and 65 nm standard processes through TSMC. Based model, EMI in inverter reduced increasing 10 MHz 4 GHz.